wafer.space Community - Ah, this reminds me I wanted to start

11:54 a.m.

The idea is that you just specify a projects.yaml listing the projects you have, as well as having each LibreLane project in its own directory, and then the tool automatically clones the template repo, generates a top-level config, generates the multiplexer verilog source and runs the flow. (edited)

11:55 a.m.

11:56 a.m.

pin mapping is a long list showing how a design’s module outputs map to the pads when selected

11:56 a.m.

You can actually map these connections arbitrarily

11:57 a.m.

Consider this design, where I wish to save on signals by not having enables for every pad

11:57 a.m.

Which I can then map like this

11:58 a.m.

If the number of outputs of a design is equal to the total number of outputs available, there is a special shorthand syntax where you just type "out" for a 1:1 mapping, such that

1: out[1]
2: out[2]
3: out[3]

is equivalent to just

1: out
2: out
3: out

11:59 a.m.

If you have less outputs, you need an explicit mapping, though

12:00 p.m.

As for inputs, there is no mapping. Every design receives all available inputs always.

12:00 p.m.

This solution has worked for me for many tapeouts

12:03 p.m.

(And, of course, the syntax of in_pu just means constant input with pull-up)

12:03 p.m.

The syntax is pretty simple. Its just a list of attributes separated by underscores

12:04 p.m.

projects.yaml

3.07 KB

12:05 p.m.

TODO: allow the placement of arbitrary macros with connections between them so you can, for instance, have SRAM macros on your multi-project die

Is there any python library I can use to help me procedurally generate code, or is there some preferred way to do this?